Название: RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design Автор: Stuart Sutherland
Издательство: Sutherland HDL, Inc.
Год: 2017
Страниц: 472
Язык: английский
Формат: pdf (true)
Размер: 11.5 MB
This book is both a tutorial and a reference for engineers who use the SystemVerilog Hardware Description Language (HDL) to design ASICs and FPGAs. The book shows how to write SystemVerilog models at the Register Transfer Level (RTL) that simulate and synthesize correctly, with a focus on proper coding styles and best practices. SystemVerilog is the latest generation of the original Verilog language, and adds many important capabilities to efficiently and more accurately model increasingly complex designs. This book reflects the SystemVerilog standards. This book is for engineers who already know, or who are learning, digital design engineering.
