Название: Design for Testability, Debug and Reliability: Next Generation Measures Using Formal TechniquesАвтор: Sebastian Huhn, Rolf Drechsler
Издательство: Springer
Год: 2021
Страниц: 177
Язык: английский
Формат: pdf (true), epub
Размер: 11.5 MB
This book introduces several novel approaches to pave the way for the next generation of integrated circuits, which can be successfully and reliably integrated, even in safety-critical applications. The authors describe new measures to address the rising challenges in the field of design for testability, debug, and reliability, as strictly required for state-of-the-art circuit designs. In particular, this book combines formal techniques, such as the Satisfiability (SAT) problem and the Bounded Model Checking (BMC), to address the arising challenges concerning the increase in test data volume, as well as test application time and the required reliability.
All methods are discussed in detail and evaluated extensively, while considering industry-relevant benchmark candidates. All measures have been integrated into a common framework, which implements standardized software/hardware interfaces.
Several improvements in the electronic design automation flow enabled the design of highly complex integrated circuits. This complexity has been introduced to address the challenging intended application scenarios, for instance, in automotive systems, which typically require several heterogeneous functions to be jointly implemented on-chip at once. On the one hand, the complexity scales with the transistor count and, on the other hand, further non-functional aspects have to be considered, which leads to new demanding tasks during the state-of-the-art IC design and test. Thus, new measures are required to achieve the required level of testability, debug, and reliability of the resulting circuit.
This book combines formal techniques - like the Boolean Satisfiability (SAT) problem and the bounded model checking - to address the arising challenges concerning the increase in Test Data Volume (TDV) as well as Test Application Time (TAT) and the required reliability.
One important part of this book concerns the introduction of Test Vector Transmitting using enhanced compression-based TAP controllers (VecTHOR). VecTHOR proposes a newly designed compression architecture, which combines a codeword-based compression, a dynamically configurable dictionary and a run-length encoding scheme. VecTHOR fulfills a lightweight character and is seamlessly integrated within an IEEE 1149.1 test access port controller.
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