Название: Multi-Gigahertz Nyquist Analog-to-Digital Converters: Architecture and Circuit Innovations in Deep-Scaled CMOS and FinFET TechnologiesАвтор: Athanasios T. Ramkaj, Marcel J.M. Pelgrom, Michiel S.J. Steyaert
Издательство: Springer
Серия: Analog Circuits and Signal Processing
Год: 2023
Страниц: 289
Язык: английский
Формат: pdf (true)
Размер: 23.6 MB
This book proposes innovative circuit, architecture, and system solutions in deep-scaled CMOS and FinFET technologies, which address the challenges in maximizing the accuracy/speed/power of multi-GHz sample rate and bandwidth Analog-to-Digital Converters (ADC)s. A new holistic approach is introduced that first identifies the major error sources of a converter’ building blocks, and quantitatively analyzes their impact on the overall performance, establishing the fundamental circuit-imposed accuracy – speed – power limits. The analysis extends to the architecture level, by introducing a mathematical framework to estimate and compare the accuracy – speed – power limits of several ADC architectures and variants. To gain system-level insight, time-interleaving is covered in detail, and a framework is also introduced to compare key metrics of interleaver architectures quantitatively. The impact of technology is also considered by adding process effects from several deep-scaled CMOS technologies.
The analog-to-digital converter (ADC) is considered the cornerstone of modern electronics due to its fundamental role in virtually any application requiring the transfer of information between the physical (analog) world and the processing (digital) world. This task comes with myriad challenges due to the complex multi-functional ADC nature, further exacerbated when the relevant applications demand stringent performance requirements. Furthermore, bridging the analog and digital worlds fundamentally implies that ADCs must deal with the non-idealities of the former while keeping up with the advancements of the latter.
The rapidly accelerating trend for broader-band signals and software-defined systems has spurred the need for ADCs operating in the multi-GHz sample rate and bandwidth regime. Such converters are highly demanded by applications in the realm of next generation high-speed wireless and wireline communications, automotive radar, and high-end instrumentation, and have attracted a growing attention from both industry and academia. The ever-increasing desire of these systems is to maximize speed, while progressively improving the accuracy and the power efficiency, pushing the performance dimensions to new benchmarks. Meeting these requirements at the multi-GHz regime comes with numerous challenges at the circuit, architecture, and system levels. On top, the constant technology downscaling, dictated by the demand for higher functionality at a reduced power and cost, and the improvement in digital performance, exacerbates these challenges for traditional analog-intensive solutions.
This book follows a holistic approach, from analysis to implementation, to propose innovative circuit, architecture, and system solutions in deep-scaled CMOS and maximize the accuracy⋅speed÷ power of multi-GHz sample rate and bandwidth ADCs. The approach starts by identifying the major error sources of any practical converter’s circuits and quantitatively analyzing their significance on the overall performance, establishing the fundamental accuracy-speed-power limits imposed by circuits, and building an understanding as to what may be achievable from a converter’s elementary building blocks. The analysis extends to the architecture level, by introducing a mathematical framework to estimate and compare the accuracy-speed-power limits of high-performance architectures, such as flash, SAR, pipeline, and pipelined-SAR. To gain insight on the system level and peripheral blocks, a framework is introduced to quantitatively compare interleaver architectures, in terms of achievable bandwidth and sampling accuracy. The strength of the newly introduced frameworks is further enhanced by adding technology effects from four deep-scaled CMOS processes: 65 nm, 40 nm, 28 nm, and 16 nm, building insight into both architecture as well as process choices for optimum performance at given specifications.
Contents:
1. Introduction
2. Analog-to-Digital Conversion Fundamentals
3. Architectural Considerations for High-Efficiency GHz-Range ADCs
4. Ultrahigh-Speed High-Sensitivity Dynamic Comparator
5. High-Speed Wide-Bandwidth Single-Channel SAR ADC
6. High-Resolution Wide-Bandwidth Time-Interleaved RF ADC
7. Ultra-Wideband Direct RF Receiver Analog Front-End
8. Conclusions, Contributions, and Future Work
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