Название: FreeRTOS on the STM32F7 microcontrollerАвтор: Kristof Mulier
Издательство: Leanpub
Год: 2021-04-23
Страниц: 176
Язык: английский
Формат: pdf (true)
Размер: 18.1 MB
The first and foremost challenge I faced when getting started with this microcontroller is finding out where to find all the documentation. There are so many companies and organizations involved that contribute to the final chip. The compiler, assembler and linker for your C-code is provided by GNU (the ARM engineers actively cooperate with GNU to maintain the toolchain). The processor core is designed by ARM. The silicon vendor STMicroelectronics designs the actual chip based on the ARM core and adds a set of peripherals. Both ARM and STMicroelectronics provide a library to interface with the chip hardware: CMSIS and ST HAL respectively. STMicroelectronics also delivers the programmer to flash your code onto the chip. And you might need a real-time operating system, provided by yet another company.
The NVIC and the processor core interface are closely coupled. All interrupts – including the core exceptions – are managed by the NVIC. To my understanding, the following model gives a correct view on how interrupts are processed. Each peripheral that can fire interrupts has a dedicated ‘interrupt line’ or ‘IRQ line’ routed to the NVIC Controller. There is no direct contact between the peripheral and the CPU. But this IRQ line provides the peripheral a way to request for an interrupt to take place. The NVIC has the responsibility to schedule the incoming interrupt requests and make the CPU execute the most important ones first. One can assume that the NVIC maintains simple ‘state machines’ for this purpose. Every peripheral starts in the inactive state – there is no request for interrupt pending. Upon a request, the peripheral goes into the pending state. It waits there until the NVIC determines that no other more important interrupts are pending. When the CPU starts executing the ISR (Interrupt Service Routine) associated with that peripheral, it is said to be active. Usually the peripheral slides back into the inactive state upon completion of the ISR code.
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