Название: Nanometer CMOS ICs: From Basics to ASICs, 3rd EditionАвтор: Harry Veendrick
Издательство: Springer
Год: 2025
Страниц: 697
Язык: английский
Формат: pdf (true)
Размер: 39.0 MB
This textbook provides a comprehensive, fully-updated introduction to the essentials of nanometer CMOS integrated circuits. It includes aspects of scaling to even beyond 3nm CMOS technologies and designs. It clearly describes the fundamental CMOS operating principles and presents substantial insight into the various aspects of design, fabrication and application. Coverage includes all associated disciplines of nanometer CMOS ICs, including physics, lithography, technology, design, memories, VLSI, power consumption, variability, reliability and signal integrity, testing, yield, failure analysis, packaging, scaling trends and road blocks. The text is based upon in-house Philips, NXP Semiconductors, Applied Materials, ASML, IMEC, ST-Ericsson, Infineon, TSMC, etc., courseware, which, to date, has been completed by more than 7000 engineers working in a large variety of the above mentioned disciplines.
An integrated circuit (IC) is a piece of semiconductor material, on which a number of electronic components are interconnected. These ‘chip’ components implement a specific function. The semiconductor material is usually silicon but alternatives include gallium arsenide (for RF devices), silicon carbide (for power electronics) and indium phosphite (for fibre optics and lasers). ICs are essential in all modern electronic products.
This book leads the reader into the magic of semiconductor nano-scale integrated devices, circuits and systems. It originates from the authors own rich research experience in IC design and decades of training and teaching the details of semiconductors. The two preceding editions of this book have already inspired tens of thousands of engineers and researchers from a multitude of companies and academic teams.
The reach of the book, from the basics of different semiconductor device families all the way up to large circuit design, is ambitious. But it reflects the importance for the innovators and engineers in the state-of-the-art semiconductor technology to have a fundamental appreciation of the full stack of disciplines that are required to build a complex system-on-chip or a specialty circuit tuned to a specific application. The fundamental understanding of the device physics and the parameters that govern the CMOS scaling into the sub-2 nm regime leads to a better understanding of reliability and variability that play at circuit and systems level. How Artificial Intelligence workloads are optimally ported on a chiplet-based heterogeneous compute architecture will be the result of an optimisation based on elevated insight in technology options for compute, memory—or compute-in-memory—, interconnect and packaging. Indeed, in advanced digital applications one can find numerous examples that illustrate the need for System-Technology Co-Optimisation.
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