Название: Circuit-Technology Co-Optimization of SRAM Design in Advanced CMOS NodesАвтор: Hsiao-Hsuan Liu, Francky Catthoor
Издательство: Springer
Год: 2025
Страниц: 293
Язык: английский
Формат: pdf (true)
Размер: 29.5 MB
Modern computing engines―CPUs, GPUs, and NPUs―require extensive SRAM for cache designs, driven by the increasing demand for higher density, performance, and energy efficiency. This book delves into two primary areas within ultra-scaled technology nodes: (1) advancing SRAM bitcell scaling and (2) exploring innovative subarray designs to enhance power-performance-area (PPA) metrics across technology nodes.
The first part of the book utilizes a bottom-up design-technology co-optimization (DTCO) approach, employing a dedicated PPA simulation framework to evaluate and identify the most promising strategies for SRAM bitcell scaling. It offers a comprehensive examination of SRAM bitcell scaling beyond 1 nm node, outlining a structured research cycle that includes identifying scaling bottlenecks, developing cutting-edge architectures with complementary field-effect transistor (CFET) technology, and addressing challenges such as process integration and routing complexities. Additionally, this book introduces a novel write margin methodology to better address the risks of write failures in resistance-dominated nodes. This methodology accounts for time-dependent parasitic bitline effects and incorporates timing setup of write-assist techniques to prevent underestimating the yield loss.
Modern computing engines, such as central processing units (CPUs), graphics processing units (GPUs), and neural processing units (NPUs), play a pivotal role in advancing general-purpose computing, Artificial Intelligence (AI), Machine Learning (ML), and Deep Learning (DL) applications. These silicon-based microprocessors necessitate substantial amounts of SRAM for level-2 (L2) and level-3 (L3) caches. For instance, the AMD CPU RyzenTM 7 5800X3D features 96-MB L3 cache, while Nvidia’s GPU GeForce RTX 4090 carries 72-MB L2 cache. The increasing demand for L2 and last-level cache (LLC) size underscores the urgency for improved on-die SRAM density, thereby exerting significant pressure to enhance speed and energy consumption metrics. Simultaneously, level-1 (L1) cache is essential for each core to store frequently accessed data and instructions, operating at the same speed as the CPU. The increasing number of on-chip cores (e.g., from 4 to 8 cores from AMD Zen 1 to Zen 4) necessitates an increase in the number of L1 caches. These L1 caches dictate CPU performance and consume a significant portion of power due to the high activity factor in modern multi-core system-on-chips (SoCs).
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